1. Field of the Invention
The present invention relates to a method for forming an insulating film between metal wirings of a semiconductor device, and more particularly to a method for forming an insulating film between metal wirings of a semiconductor device, which involves treating a patterned surface of a semiconductor substrate using plasma, forming a first intermetal insulating film on the plasma-treated substrate surface in accordance with a plasma enhanced chemical vapor deposition (PECVD) method, and then forming an O.sub.3 -tetra ethyl ortho silicate (TEOS) film on the insulating film.
2. Description of the Prior Art
An increase in the integration degree of semiconductor devices results in a reduction in the width of conduction wirings such as gate electrodes or bit lines. As such conduction wirings have a reduced width, their electrical resistance increases correspondingly. For example, if the width of a conduction wiring is reduced by a time of 1/N, the electrical resistance generated at the conduction wiring increases by N times. Such an increase in electrical resistance results in a decrease in the operating speed of the semiconductor device.
For conduction wirings used as gate or bit lines of semiconductor devices, doped polysilicon layers are typically used. However, such doped polysilicon layers exhibit a high surface resistance of about 30 to 70 .OMEGA./cm.sup.2 and a high contact resistance of about 30 to 70 .OMEGA./cm.sup.2 per contact.
Such high surface and contact resistances serve to decrease the operating speed of the semiconductor device. In order to decrease such resistances, a selective metal film deposition method has been proposed, which provides a silicide, namely, self-aligned silicide structure consisting of a metal-silicide film formed over a polysilicon layer. In accordance with this method, a metal silicide film or selective metal film is formed only over the conduction wiring.
For example, where a titanium silicide or selective tungsten layer is formed over a polysilicon layer pattern, it is possible to considerably reduce the surface resistance to about 5 .OMEGA./cm.sup.2 and the contact resistance to about 3 .OMEGA./cm.sup.2 or below per contact. Accordingly, a lengthened operating time of semiconductor devices is obtained. It is also possible to achieve a high integration of semiconductor devices.
Typically, aluminum or an alloy thereof is used to form metal wirings. In order to obtain an improved characteristic, the use of tungsten has also been proposed. As compared to aluminum, tungsten exhibits a superior stability at a high temperature, provides a thin metal wiring and achieves an easy planarization.
Referring to FIGS. 1A to 1C, a conventional method for forming an insulating film between metal wirings of a semiconductor device is illustrated. For convenience of description, the metal wirings will be described as consisting of tungsten.
In accordance with this method, a semiconductor substrate (not shown) is first prepared, which is provided with an elementisolating oxide film to define an active region. The semiconductor substrate is also provided with MOS transistors, capacitors and bit lines. Over the entire surface of the semiconductor substrate, an insulating film 1 is then formed, as shown in FIG. 1A.
On the insulating film 1, a Ti layer 2 and a TiN layer 3 are sequentially formed to form a barrier metal layer. A tungsten (W) layer 4 is then deposited over the TiN layer 3 in accordance with the well-know chemical vapor deposition (CVD) method. Thereafter, an anti-reflection film 5 made of TiN is formed over the W layer 4. The anti-reflection film 5 serves to prevent an irregular reflection phenomenon occurring when the W layer is subsequently exposed to light for its patterning.
Thereafter, the resulting structure is wet or dry-etched from the anti-reflection film 5 to the Ti layer 2 in a sequential manner in accordance with the well-known photo-etching method, thereby forming metal wirings consisting of the conduction patterns from the pattern of the anti-reflection film 5 to the pattern of the Ti layer 2.
Over the entire surface of the resulting structure, an oxide film 6 is formed to a thickness of about 1,000 .ANG. in accordance with the well-known CVD method, as shown in FIG. 1B. The oxide film 6 is then exposed at its surface to Ar or N.sub.2 gas plasma, thereby causing the surface to be damaged while generating charge. This step is carried out to achieve an improvement in the interface characteristic of the oxide film 6 with a planarizing layer which will be subsequently formed.
An O.sub.3 -TEOS film 7 is then formed over the surface-damaged oxide film 6, as shown in FIG. 1C. In order to provide a planarized surface, the material of the O.sub.3 -TEOS film 7 flows. Thus, an insulating film between metal wirings is formed.
As mentioned above, the conventional method involves the steps of forming an oxide film over metal wirings, plasma-treating the surface of the oxide film, thereby damaging the oxide film surface, and forming an O.sub.3 -TEOS film as a planarizing film over the surface-damaged oxide film. However, the O.sub.3 -TEOS film is grown at a growth rate varying depending on the kind or condition of the under layer disposed therebeneath because it exhibits a high dependency on the under layer. In some cases, the O.sub.3 -TEOS film may have a plurality of voids or exhibit a degraded flowability and reproducibility. As a result, the conventional method has problems such as a degraded yield and reliability.
Where the metal wirings consist of tungsten in place of aluminum, the growth rate of the O.sub.3 -TEOS film decreases greatly, thereby resulting in a degradation in the quality of the film.